Clock CK1 is also going to the clock pins of flops in block 2. This command specifies the period, duty cycle, rise and fall edges of a clock. Hence are defined using create_clock command at respective pins. At pin IO2 of block A and pin IO6 of block B, the clocks are entering the blocks. These clocks must be defined in the timing constraints.
As there are two PLLs in the above design, it is clear that there are two different clocks in the design. I/O Pins 2, 6, 10 – Clocks are the most important part of a design. Design constraints will be defined at the I/O pins. Two PLLs serve two different clocks to the design. There are two blocks in the design named block A and block B. The aim of this blog is to understand how SDC file is written for a design. We will not look at the syntax of SDC commands.
We will understand the design constraints with reference to the following figure. Objects can be design, clock, port, pin, cell, net, library, etc. The information specified in design constraints is operating conditions, wire load models, system interface, design rule constraints, timing constraints, timing exceptions, area constraints, multi-voltage & power optimization constraints and logic assignments.ĭesign constraints will have all the object access commands. SDC file contains the following information: SDC is based on the tool command language (Tcl). This format is used by different EDA tools to synthesize and analyse a design. The Synopsys Design Constraints (SDC) format is used to specify the design intent, including timing, power and area constraints for a design.
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